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for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the max5621/max5622/max5623 are 16-bit digital-to- analog converters (dacs) with 16 sample-and-hold (sha) outputs for applications where a high number of programmable voltages are required. these devices include a clock oscillator and a sequencer that updates the dac with codes from an internal sram. no external components are required to set offset and gain. the max5621/max5622/max5623 feature a -4.5v to +9.2v output voltage range. other features include a 200?/step resolution, with output linearity error, typi- cally 0.005% of full-scale range (fsr). the 100khz refresh rate updates each sha every 320?, resulting in negligible output droop. remote ground sensing allows the outputs to be referenced to the local ground of a separate device. these devices are controlled through a 20mhz spi/qspi/microwire-compatible 3-wire serial interface. immediate update mode allows any channel? output to be updated within 20?. burst mode allows multiple values to be loaded into memory in a single, high-speed data burst. all channels are updated within 330? after data has been loaded. each device features an output clamp and output resis- tors for filtering. the max5621 features a 50 ? output impedance and is capable of driving up to 250pf of out- put capacitance. the max5622 features a 500 ? output impedance and is capable of driving up to 10nf of output capacitance. the max5623 features a 1k ? output imped- ance and is capable of driving up to 10nf of output capacitance. the max5621/max5622/max5623 are available in 64-pin tqfp (12mm x 12mm) and 68-pin thin qfn (10mm x 10mm) packages. ________________________applications mems mirror servo control industrial process control automatic test equipment instrumentation features ? integrated 16-bit dac and 16-channel sha with sram and sequencer ? 16 voltage outputs ? 0.005% output linearity ? 200v output resolution ? flexible output voltage range ? remote ground sensing ? fast sequential loading: 1.3s per register ? burst and immediate mode addressing ? no external components required for setting gain and offset ? integrated output clamp diodes ? three output impedance options max5621 (50 ? ), max5622 (500 ? ), and max5623 (1k ? ) 19-2715; rev 2; 1/06 max5621/max5622/max5623 16-bit dacs with 16-channel sample-and-hold outputs ________________________________________________________________ maxim integrated products 1 pin configurations ordering information spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor, corp. part pin-package pkg code max5621 ucb 64 tqfp c64-8 max5621utk 68 thin qfn-ep* t6800-3 max5622 ucb 64 tqfp c64-8 max5622utk 68 thin qfn-ep* t6800-3 max5623 ucb 64 tqfp c64-8 max5623utk 68 thin qfn-ep* t6800-3 pin configurations continued at end of data sheet. 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 thin qfn top view 52 53 35 36 37 48 49 50 64 65 66 67 23 22 21 20 19 27 26 25 24 18 29 28 32 33 31 30 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 max5621 max5622 max5623 eclk out0 v ref agnd n.c. out15 n.c. out14 n.c. out13 agnd n.c. out12 n.c. out11 n.c. cl cl out1 n.c. out2 n.c. agnd n.c. n.c. out3 n.c. out4 ch out5 v ss 34 n.c. ch v ss out10 n.c. out9 n.c. out8 agnd v dd n.c. out7 n.c. out6 n.c. cl immed v logic sclk din cs v ss 17 n.c. agnd v lsha dgnd clksel rst v ldac gs n.c. v dd 51 n.c. n.c. ch 68 n.c. v dd * ep = exposed pad. note: all devices specified over 0? to +85? operating range. for other t emperature ranges, contact factory.
max5621/max5622/max5623 16-bit dacs with 16-channel sample-and-hold outputs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +10v, v ss = -4v, v logic = v ldac = v lsha = +5v, v ref = +2.5v, agnd = dgnd = v gs = 0v, r l 10m ? , c l = 50pf, clksel = +5v, f eclk = 400khz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd.......................................................-0.3v to +12.2v v ss to agnd .........................................................-6.0v to +0.3v v dd to v ss ...........................................................................+15v v ldac , v logic , v lsha to agnd or dgnd ..............-0.3v to +6v ref to agnd............................................................-0.3v to +6v gs to agnd................................................................v ss to v dd cl and ch to agnd...................................................v ss to v dd logic inputs to dgnd ..............................................-0.3v to +6v dgnd to agnd........................................................-0.3v to +2v maximum current into out_ ............................................?0ma maximum current into logic inputs .................................?0ma continuous power dissipation (t a = +70?) 64-pin tqfp (derate 13.3mw/? above +70?) ............1066mw 68-pin thin qfn (derate 28.6mw/? above +70?) ......2285mw operating temperature range...............................0? to +85? maximum junction temperature .....................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units dc characteristics resolution n 16 bits output range v out_ (note 1) v ss + 0.75 v dd - 2.4 v offset voltage code = 4f2c hex 15 200 mv offset voltage tempco 50 ?/? gain error (note 2) ? % gain tempco 5 ppm/? integral linearity error inl v out_ = -3.25v to +7.6v 0.005 0.015 %fsr differential linearity error dnl v out_ = -3.25v to +7.6v; monotonicity guaranteed to 14 bits 1 4 lsb maximum output drive current i out sinking and sourcing 2ma max5621 35 50 65 max5622 350 500 650 dc output impedance r out max5623 700 1000 1300 ? max5621 250 pf max5622 10 maximum capacitive load max5623 10 nf dc crosstalk internal oscillator enabled (note 3) -90 db power-supply rejection ratio psrr internal oscillator enabled -80 db
max5621/max5622/max5623 16-bit dacs with 16-channel sample-and-hold outputs _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +10v, v ss = -4v, v logic = v ldac = v lsha = +5v, v ref = +2.5v, agnd = dgnd = v gs = 0v, r l 10m ? , c l = 50pf, clksel = +5v, f eclk = 400khz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units dynamic characteristics sample-and-hold settling (note 4) 0.08 % sclk feedthrough 0.5 nv-s f seq feedthrough 0.5 nv-s hold-step 0.25 1mv droop rate v out_ = 0v (note 5), t a = +25? 1 40 mv/s output noise 250 ? rms reference input input resistance 7k ? reference input voltage v ref 2.5 v ground-sense input input voltage range v gs -0.5 +0.5 v input bias current i gs -0.5v v gs +0.5v -60 0 a gs gain (note 6) 0.998 1 1.002 v/v digital interface dc characteristics input high voltage v ih 2.0 v input low voltage v il 0.8 v input current 1a timing characteristics (figure 2) sequencer clock frequency f seq internal oscillator 80 100 120 khz external clock frequency f eclk (note 7) 480 khz sclk frequency f sclk 20 mhz sclk pulse width high t ch 15 ns sclk pulse width low t cl 15 ns cs low to sclk high setup time t csso 15 ns cs high to sclk high setup time t css1 15 ns sclk high to cs low hold time t csh0 10 ns
max5621/max5622/max5623 16-bit dacs with 16-channel sample-and-hold outputs 4 _______________________________________________________________________________________ note 1: the nominal zero-scale (code = 0) voltage is -4.0535v. the nominal full-scale (code = ffff hex) voltage is +9.0535v. the output voltage is limited by the output range specification, restricting the usable range of dac codes. the nominal zero- scale voltage can be achieved when v ss < -4.9v, and the nominal full-scale voltage can be achieved when v dd > +11.5v. note 2: gain is calculated from measurements: for voltages v dd = 10v and v ss = -4v at codes c000 hex and 4f2c hex for voltages v dd = 11.6v and v ss = -2.9v at codes ffff hex and 252e hex for voltages v dd = 9.25v and v ss = -5.25v at codes d4f6 hex and 0 hex for voltages v dd = 8.55v and v ss = -2.75v at codes c74a hex and 281c hex note 3: steady-state change in any output with an 8v change in an adjacent output. note 4: settling during the first update for an 8v step. the output settles to within the linearity specification on subsequent updates . tested with an external sequencer clock frequency of 480khz. note 5: external clock mode with the external clock not toggling. note 6: the output voltage is the sum of the dac output and the voltage at gs. gs gain is measured at 4f2c hex. note 7: the sequencer runs at f seq = f eclk /4. maximum speed is limited by settling of the dac and shas. minimum speed is limited by acceptable droop and update time after a burst mode update. note 8: v dd rise to cs low = 500? maximum. note 9: guaranteed by gain-error test. note 10: the serial interface is inactive. v ih = v logic , v il = 0v. note 11: the serial interface is active. v ih = v logic , v il = 0v. electrical characteristics (continued) (v dd = +10v, v ss = -4v, v logic = v ldac = v lsha = +5v, v ref = +2.5v, agnd = dgnd = v gs = 0v, r l 10m ? , c l = 50pf, clksel = +5v, f eclk = 400khz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units sclk high to cs high hold time t csh1 0ns din to sclk high setup time t ds 15 ns din to sclk high hold time t dh 0ns rst to cs low (note 8) 500 ? power supplies positive supply voltage v dd (note 9) 8.55 10 11.60 v negative supply voltage v ss (note 9) -5.25 -4 -2.75 v supply difference v dd - v ss (note 9) 14.5 v logic supply voltage v logic , v ldac , v lsha 4.75 5 5.25 v positive supply current i dd 32 42 ma negative supply current i ss 32 40 ma (note 10) 1 1.5 logic supply current i logic f sclk = 20mhz (note 11) 2 3 ma
-0.007 -0.003 -0.005 0.001 -0.001 0.005 0.003 0.007 4018 19520 27271 11769 35021 42723 58268 integral nonlinearity vs. code max5621 toc01 input code integral nonlinearity (%) -1.4 -0.6 -1.0 0.2 -0.2 1.0 0.6 1.4 differential nonlinearity vs. code max5621 toc02 input code differential nonlinearity (lsb) 4018 19520 27271 11769 35021 42723 58268 0 0.002 0.006 0.004 0.008 0.010 -40 10 -15 35 60 85 integral nonlinearity vs. temperature max5621 toc03 temperature ( c) integral nonlinearity (%) 0.5 0.6 0.8 0.7 0.9 1.0 -40 10 -15 35 60 85 differential nonlinearity vs. temperature max5621 toc04 temperature ( c) differential nonlinearity (lsb) -20 -18 -14 -16 -12 -10 -40 10 -15 35 60 85 offset voltage vs. temperature max5621 toc05 temperature ( c) offset voltage (mv) v dd = +8.55v v ss = -4v code = 4f2c hex droop rate vs. temperature temperature ( c) -40 35 60 -15 10 85 droop rate (mv/s) 100 0.0001 0.001 0.010 0.100 10 1 max5621 toc06 code = 4f2c hex external clock mode no clock applied 0 0.01 0.03 0.02 0.04 0.05 -40 10 -15 35 60 85 gain error vs. temperature max5621 toc07 temperature ( c) gain error (%) code = c168 hex offset code = 4f2c hex 10 100 0 -10 -20 -30 -40 -60 -50 -70 -80 0.01 0.1 1 positive supply psrr vs. frequency max5621 toc08 frequency (khz) psrr (db) -90 -90 0 0.001 0.01 0.1 1 10 100 negative supply psrr vs. frequency -10 -20 max5621 toc09 frequency (khz) psrr (db) -40 -30 -70 -80 -60 -50 typical operating characteristics (v dd = +10v, v ss = -4v, v ref = +2.5v, v gs = 0v, t a = +25?, unless otherwise noted.) max5621/max5622/max5623 16-bit dacs with 16-channel sample-and-hold outputs _______________________________________________________________________________________ 5
max5621/max5622/max5623 16-bit dacs with 16-channel sample-and-hold outputs 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v dd = +10v, v ss = -4v, v ref = +2.5v, v gs = 0v, t a = +25?, unless otherwise noted.) 400 500 700 600 800 900 logic supply current vs. logic supply voltage max5621 toc10 logic supply voltage (v) logic supply current ( a) 4.75 5.25 5.00 5.50 interface inactive 0 400 200 800 600 1000 1200 logic supply current vs. logic input high voltage max5621 toc11 logic input high voltage (v) logic supply current ( a) 2.0 3.0 3.5 2.5 4.0 4.5 5.0 f sclk = 20mhz 20 22 24 26 28 30 32 34 36 -40 -15 10 35 60 85 supply current vs. temperature max5621 toc12 temperature ( c) supply current (ma) i ss i dd interface inactive positive settling time (8v step) max5621 toc13 v out_ eclk 0v 5v/div 3.5v 1 s/div negative settling time (8v step) max5621 toc14 v out_ eclk 0v 5v/div 3.5v 1 s/div positive settling time (100mv step) max5621 toc15 v out_ eclk 0v 50mv/div ac-coupled 3.5v 1 s/div negative settling time (100mv step) max5621 toc16 v out_ eclk 0v 50mv/div ac-coupled 3.5v 1 s/div output noise max5621 toc17 out_ 1mv/div 250 s/div
max5621/max5622/max5623 16-bit dacs with 16-channel sample-and-hold outputs _______________________________________________________________________________________ 7 pin description pin tqfp thin qfn name function 1, 2, 20, 22, 24, 27, 29, 34, 36, 38, 42, 44, 50, 52, 54, 57, 59, 61 1, 2, 17, 21, 23, 25, 28, 30, 34, 36, 38, 40, 44, 46, 51, 53, 55, 57, 60, 62, 64, 68 n.c. no connection. not internally connected. 3 3 gs ground-sensing input 44v ldac +5v dac power supply 55 rst reset input 66 cs chip-select input 7 7 din serial data input 8 8 sclk serial clock input 99v logic +5v logic power supply 10 10 immed immediate update mode 11 11 eclk external sequencer clock input 12 12 clksel clock-select input 13 13 dgnd digital ground 14 14 v lsha +5v sample-and-hold power supply 15, 25, 40, 55, 62 15, 26, 42, 58, 65 agnd analog ground 16, 32, 46 16, 33, 48 v ss negative power supply 17, 39, 48 18, 41, 50 v dd positive power supply 18, 33, 49 19, 35, 52 cl output clamp low voltage 19 20 out0 output 0 21 22 out1 output 1 23 24 out2 output 2 26 27 out3 output 3 28 29 out4 output 4 30 31 out5 output 5 35 37 out6 output 6 37 39 out7 output 7 41 43 out8 output 8 43 45 out9 output 9 45 47 out10 output 10 31, 47, 64 32, 49, 67 ch output clamp high voltage 51 54 out11 output 11 53 56 out12 output 12 56 59 out13 output 13 58 61 out14 output 14 60 63 out15 output 15 63 66 ref reference voltage input
max5621/max5622/max5623 16-bit dacs with 16-channel sample-and-hold outputs 8 _______________________________________________________________________________________ figure 1. functional diagram clock eclk clksel sequencer serial interface last address sequential address 16-bit dac gain and offset correction 16 x 16 sram cs sclk din addr select write enable data ready read enable ch cl ref gs out0 out15 sample d[15:0] immed rst 2:1 m u x r e g i s t e r r e g i s t e r sample- and-hold array max5621 max5622 max5623 t csho t ch t csso t cl t dh t ds t csh1 t css1 cs sclk din b23 b22 b0 figure 2. serial interface timing diagram
max5621/max5622/max5623 16-bit dacs with 16-channel sample-and-hold outputs _______________________________________________________________________________________ 9 detailed description digital-to-analog converter the max5621/max5622/max5623 16-bit digital-to-ana- log converters (dacs) are composed of two matched sections. the four msbs are derived through 15 identi- cal matched resistors and the lower 12 bits are derived through a 12-bit inverted r-2r ladder. sample-and-hold amplifiers the max5621/max5622/max5623 contain 16 buffered sample/hold circuits with internal hold capacitors. internal hold capacitors minimize leakage current, dielectric absorption, feedthrough, and required board space. the max5621/max5622/max5623 provide a very low 1mv/s droop rate. output the max5621/max5622/max5623 include output buffers on each channel. the device contains output resistors in series with the buffer output (figure 3) for ease of output filtering and capacitive load driving stability. output loads increase the analog supply current (i dd and i ss ). excessively loading the outputs drastically increases power dissipation. do not exceed the maxi- mum power dissipation specified in the absolute maximum ratings . the maximum output voltage range depends on the analog supply voltages available and the output clamp voltages (see the output clamp section): the device has a fixed theoretical output range deter- mined by the reference voltage, gain, and midscale offset. the output voltage for a given input code is calculated with the following: where code is the decimal value of the dac input code, v ref is the reference voltage, and v gs is the voltage at the ground-sense input. with a 2.5v refer- ence, the nominal end points are -4.0535v and +9.0535v (table 1). note that these are ?irtual?inter- nal end-point voltages and cannot be reached with all combinations of negative and positive power-supply voltages. the nominal, usable dac end-point codes for the selected power supplies can be calculated as: lower end-point code = 32768 - ((2.5v - (v ss +0.75) / 200?) (result 0) upper end-point code = 32768 + ((v dd - 2.4 - 2.5v) / 200?) (result 65535) v code v v out ref gs = ? ? ? ? ? ? () + 65535 5 2428 . - 1.6214 v ref vvvvv ss out dd + () ? () 075 24 .. _ - table 1. code table dac input code msb lsb nominal output voltage (v) v ref = +2.5v 1111 1111 1111 1111 9.0535 full-scale output 1100 0111 0100 1010 6.15 maximum output with v dd = 8.55v 1000 0000 0000 0000 2.5 midscale output 0100 1111 0010 1100 0 v out_ = 0; all outputs default to this code after power-up 0010 1000 0001 1100 -2.0 minimum output with v ss = -2.75v 0000 0000 0000 0000 -4.0535 zero-scale output figure 3. analog block diagram gs dac data ch out_ gain and offset c hold v ref r o one of 16 sha channels 16-bit dac r l cl a v = 1
max5621/max5622/max5623 16-bit dacs with 16-channel sample-and-hold outputs 10 ______________________________________________________________________________________ the resistive voltage-divider formed by the output resis- tor (r o ) and the load impedance (r l ), scales the out- put voltage. determine v out_ as follows: ground sense the max5621/max5622/max5623 include a ground- sense input (gs), which allows the output voltages to be referenced to a remote ground. the voltage at gs is added to the output voltage with unity gain. note that the resulting output voltage must be within the valid output voltage range set by the power supplies. output clamp the max5621/max5622/max5623 clamp the output between two externally applied voltages. internal diodes at each channel restrict the output voltage to: the clamping diodes allow the max5621/max5622/ max5623 to drive devices with restricted input ranges. the diodes also allow the outputs to be clamped during power-up or fault conditions. to disable output clamping, connect ch to v dd and cl to v ss , setting the clamping voltages beyond the maximum output voltage range. serial interface the max5621/max5622/max5623 are controlled by an spi/qspi/microwire-compatible 3-wire interface. serial data is clocked into the 24-bit shift register in an msb-first format, with the 16-bit dac data preceding the 4-bit sram address, required zero bit, 2-bit control, and a fill 0 (figure 4). the input word is framed by cs . the first rising edge of sclk after cs goes low clocks in the msb of the input word. when each serial word is complete, the value is stored in the sram at the address indicated and the control bits are saved. note that data can be corrupted if cs is not held low for an integer multiple of 24 bits. all of the digital inputs include schmitt-trigger buffers to accept slow-transition interfaces. their switching thresh- old is compatible with ttl and most cmos logic levels. serial input data format and control codes the 24-bit serial input format, shown in figure 4, compris- es 16 data bits (d15?0), 4 address bits (a3?0), 1 required zero bit after the address bits, 2 control bits (c1, c0), and a fill zero. the address code selects the output channel as shown in table 2. the control code configures the device as follows: 1) if c1 = 1, immediate update mode is selected. if c1 = 0, burst mode is selected. 2) if c0 = 0, the internal sequencer clock is selected. if c0 = 1, the external sequencer clock is selected. this must be repeated with each data word to main- tain external input. the operating modes can also be selected externally through clksel and immed. in the case where the control bit in the serial word and the external signal conflict, the signal that is a logic 1 is dominant. vvvvv ch out cl + () ? () ? 07 07 .. _ scaling factor r rr v v scaling factor l lo out chold = + = _ data address control d15 d14 d13 d12 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d0 a3 a2 a1 a0 0 c1 c0 0 msb lsb figure 4. input word sequence a3 a2 a1 a0 output 0 0 0 0 out0 selected 0 0 0 1 out1 selected 0 0 1 0 out2 selected 0 0 1 1 out3 selected 0 1 0 0 out4 selected 0 1 0 1 out5 selected 0 1 1 0 out6 selected 0 1 1 1 out7 selected 1 0 0 0 out8 selected 1 0 0 1 out9 selected 1 0 1 0 out10 selected 1 0 1 1 out11 selected 1 1 0 0 out12 selected 1 1 0 1 out13 selected 1 1 1 0 out14 selected 1 1 1 1 out15 selected table 2. channel/output selection
max5621/max5622/max5623 16-bit dacs with 16-channel sample-and-hold outputs ______________________________________________________________________________________ 11 modes of operation the max5621/max5622/max5623 feature three modes of operation: sequence mode immediate update mode burst mode sequence mode sequence mode is the default operating mode. the internal sequencer continuously scrolls through the sram, updating each of the 16 shas. at each sram address location, the stored 16-bit dac code is loaded to the dac. once settled, the dac output is acquired by the corresponding sha. using the internal sequencer clock, the process typically takes 320? to update all 16 shas (20? per channel). using an exter- nal sequencer clock the update process takes 128 clock cycles (eight clock cycles per channel). immediate update mode immediate update mode is used to change the con- tents of a single sram location, and update the corre- sponding sha output. in immediate update mode, the selected output is updated before the sequencer resumes operation. select immediate update mode by driving either immed or c1 high. the sequencer is interrupted when cs is taken low. the input word is then stored in the proper sram address. the dac conversion and sha sample in progress are completed transparent to the serial bus activity. the sram location of the addressed channel is then modi- fied with the new data. the dac and sha are updated with the new voltage. the sequencer then resumes scrolling at the interrupted sram address. this operation can take up to two cycles of the sequencer clock. up to one cycle is needed to allow the sequencer to complete the operation in progress before it is freed to update the new channel. an additional cycle is required to read the new data from memory, update the dac, and strobe the sample-and-hold. the sequencer resumes scrolling from the location at which it was interrupted. normal sequencing is suppressed while loading data, thus preventing other channels from being refreshed. under conditions of extremely frequent immediate updates (i.e., 1000 successive updates), unacceptable droop can result. figure 5 shows an example of an immediate update operation. in this example, data for channel 12 is loaded while channel 7 is being refreshed. the sequencer operation is interrupted, and no other chan- nels are refreshed as long as cs is held low. once cs returns high, and the remainder of an f seq period (if any) has expired, channel 12 is updated to the new data. once channel 12 has been updated, the sequencer resumes normal operation at the interrupted channel 7. burst mode burst mode allows multiple sram locations to be loaded at high speed. during burst mode, the output voltages are not updated until the data burst is com- plete and control returns to the sequencer. select burst mode by driving both immed and c1 low. the sequencer is interrupted when cs is taken low. all or part of the memory can be loaded while cs is low. each data word is loaded into its specified sram address. the dac conversion and sha sample in progress are completely transparent to the serial bus activity. when cs is taken high, the sequencer resumes scrolling at the interrupted sram address. new values are updated when their turn comes up in the sequence. after burst mode is used, it is recommended that at least one full sequencer loop (320?) is allowed to occur before the serial port is accessed again. this ensures that all outputs are updated before the sequencer is interrupted. update mode update time immediate update mode 2/f seq burst mode 33/f seq table 3. update mode 7 123 skip 12 7 8 9 24-bit word cs din channel 12 updated interrupted channel refreshed 2/f seq load address 12 sha array update sequence figure 5. immediate update mode timing example
max5621/max5622/max5623 figure 6 shows an example of a burst mode operation. as with the immediate update example, cs falls while channel 7 is being refreshed. data for multiple chan- nels is loaded, and no channels are refreshed as long as cs remains low. once cs returns high, sequencing resumes with channel 7 and continues normal refresh operation. thirty-three f seq cycles are required before all channels have been updated. external sequencer clock an external clock can be used to control the sequencer, altering the output update rate. the sequencer runs at 1/4 the frequency of the supplied clock (eclk). the external clock option is selected by driving either c0 or clksel high. when clksel is asserted, the internal clock oscillator is disabled. this feature allows synchronizing the sequencer to other system operations, or shutting down of the sequencer altogether during high-accuracy sys- tem measurements. the low 1mv/s droop of these devices ensures that no appreciable degradation of the output voltages occurs, even during extended periods of time when the sequencer is disabled. power-on reset a power-on reset (por) circuit sets all channels to 0v (code 4f2c hex) in sequence, requiring 320?. this pre- vents damage to downstream ics due to arbitrary refer- ence levels being presented following system power-up. this same function is available by driving rst low. during the reset operation, the sequencer is run by the internal clock, regardless of the state of clksel. the reset process cannot be interrupted, and serial inputs are ignored until the entire reset process is complete. applications information power supplies and bypassing grounding and power-supply decoupling strongly influ- ence device performance. digital signals may couple through the reference input, power supplies, and ground connection. proper grounding and layout can reduce digital feedthrough and crosstalk. at the device level, a 0.1? capacitor is required for the v dd , v ss , and v l_ pins. they should be placed as close to the pins as possible. more substantial decoupling at the board level is recommended and is dependent on the number of devices on the board (figure 7). the max5621/max5622/max5623 have three separate +5v logic power supplies, v ldac , v logic , and v lsha . v ldac powers the 16-bit digital-to-analog converter, v lsha powers the control logic of the sha array, and v logic powers the serial interface, sequencer, internal clock and sram. additional filtering of v ldac and v lsha improves the overall performance of the device. 16-bit dacs with 16-channel sample-and-hold outputs 12 ______________________________________________________________________________________ skip 6 7 skip skip 7 8 5 6 cs din 33/f seq to update all channels 2/f seq load multiple addresses sha array update sequence 7 figure 6. burst mode timing example figure 7. typical operating circuit cs din sclk immed clksel ref gs rst eclk v logic v ldac v lsha 0.1 f +5v 0.1 f +10v v dd max5621 max5622 max5623 out15 out0 out1 dgnd agnd 0.1 f v ss cl +2.5v -4v
chip information transistor count: 16,229 process: bicmos max5621/max5622/max5623 16-bit dacs with 16-channel sample-and-hold outputs ______________________________________________________________________________________ 13 pin configurations (continued) 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 eclk out0 v ref tqfp top view agnd n.c. out15 n.c. out14 n.c. out13 agnd n.c. 52 53 49 50 51 out12 n.c. out11 n.c. cl cl out1 n.c. out2 n.c. agnd n.c. n.c. out3 n.c. out4 ch out5 v ss ch v ss out10 n.c. out9 n.c. out8 agnd v dd n.c. 33 34 35 36 37 out7 n.c. out6 n.c. cl immed v logic sclk din cs v ss agnd v lsha dgnd clksel rst v ldac gs n.c. 48 v dd n.c. 64 ch v dd 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 17 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 max5621 max5622 max5623
max5621/max5622/max5623 16-bit dacs with 16-channel sample-and-hold outputs 14 ______________________________________________________________________________________ 64l tqfp.eps b 1 2 21-0083 package outline, 64l tqfp, 10x10x1.4mm b 2 2 21-0083 package outline, 64l tqfp, 10x10x1.4mm package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
max5621/max5622/max5623 16-bit dacs with 16-channel sample-and-hold outputs ______________________________________________________________________________________ 15 68l qfn thin.eps package outline 21-0142 2 1 d 68l thin qfn, 10x10x0.8mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
max5621/max5622/max5623 16-bit dacs with 16-channel sample-and-hold outputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2006 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) package outline 21-0142 2 2 d 68l thin qfn, 10x10x0.8mm

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